1. Field of the Invention
The present invention relates to a bit clock regeneration circuit, and more specifically to a bit dock regeneration circuit for use in a receiver for PCM (pulse code modulation) data and the like.
2. Description of Related Art
Referring to FIG. 1A, there is shown a typical example of a conventional bit clock regeneration circuit, which can be used in a receiver for PCM data or the like, for the purpose of regenerating a bit clock from an asynchronous input data so that the input data can be decoded on the basis of the regenerated bit clock. The shown bit flock regeneration circuit includes a T/2 pulse generator 1, an exclusive-OR circuit 5, a loop filter and voltage comparator 9, a reference voltage 10, a voltage controlled oscillator 11, a 1/2 frequency divider (divided-by-two frequency divider) 12, D-type flipflops 13 and 15, and a time constant adjusting circuit 14, which are connected as shown in FIG. 1A.
For example, as shown in FIG. 1B, the T/2 pulse generator 1 includes an exclusive-OR circuit 4 having a first input directly receiving an input data signal 101, a buffer 19 in the form of an inverter also receiving the input data signal 101, and another buffer 21 in the form of an inverter receiving an output of the buffer 19 through a delay circuit 20, an output of the buffer 21 being connected to a second input of the exclusive-OR circuit 4.
FIGS. 2, 3 and 4 are timing charts for illustrating an operation of the circuit shown in FIG. 1A. In FIGS. 2, 3 and 4, each of waveforms designated by the three-digit Reference Numerals depicts a change of the signal appearing on a point designated by the same Reference Numeral in FIG. 1A.
As seen from FIG. 1A, the input data signal 101 as shown at A in FIG. 2 is supplied to the T/2 pulse generator 1 and a data input of the D-type flipflop 15. In the T/2 pulse generator 1, as will be understood from FIG. 1B, the input data signal 101 is delayed by one half of a minimum pulse width T of the input data signal 101, by action of the buffers 19 and 21 and the delay circuit 20, so that a delayed input data signal 102 is generated as shown at B in FIG. 2. As a result, the exclusive-OR circuit 4 and hence the T/2 pulse generator 1 generates a pulse 103 which rises up at both a rising edge and a falling edge of the input data signal 101, as shown at C in FIG. 2. This pulse 103 is applied to one input of the exclusive-OR circuit 5.
On the other hand, the voltage controlled oscillator 11 generates an oscillation output signal 104 having a frequency (2/T) that is double that of the frequency corresponding to a reciprocal of the minimum pulse width T, as shown at D in FIG. 2. This oscillation output signal 104 is supplied to a 1/2 frequency divider 12, which in turn generates a frequency divided signal 105 having the frequency (1/T) corresponding to the reciprocal of the minimum pulse width T, as shown at E in FIG. 2. This frequency divided signal 105 is supplied to another input of the exclusive-OR circuit 5.
Thus, the exclusive-OR circuit 5 compares the pulse signal 103 with the pulse signal 105 in phase, and generates a pulse signal 106 indicative of a phase difference (.theta.), as shown at F in FIG. 2. This pulse signal 106 is supplied to the loop filter and voltage comparator 9, in which the pulse signal 106 is smoothened so as to generate a mean voltage signal in proportion to the phase difference, and the mean voltage signal is compared with the reference voltage 10 so as to generate a comparison result voltage signal 108 as shown at G in FIG. 2. This comparison result voltage signal 108 is applied to a control input of the voltage controlled oscillator 11 so as to control the oscillation frequency of the voltage controlled oscillator 11. Incidentally, the time constant of the voltage controlled oscillator 11 is controlled by the time constant adjusting circuit 14.
Thus, by action of the above mentioned phase synchronizing system, the oscillation frequency of the voltage controlled oscillator 11 is controlled to always follow the rate of the input data signal 101.
As seen from the above description, the above mentioned phase synchronizing system is such that the edge of the input data signal 101 is detected for the phase comparison. Accordingly, if the rate of the input data signal 101 is slow in relation to the frequency-divided signal 105 outputted from the 1/2 frequency-divider 12, as shown at A and B in FIG. 3, the pulse width in the output 106 of the exclusive-OR circuit 5 becomes narrow as shown at C in FIG. 3, so that the comparison result voltage signal 108 between the mean voltage signal in proportion to the phase difference and the reference voltage 10 is apt to relatively decrease its level as shown at D in FIG. 3.
On the other hand, if the rate of the input data signal 101 is fast in relation to the frequency-divided signal 105 outputted from the 1/2 frequency-divider 12, as shown at A and B in FIG. 4, the pulse width in the output 106 of the exclusive-OR circuit 5 becomes wide as shown at C in FIG. 4, so that the comparison result voltage signal 108 between the mean voltage signal in proportion to the phase difference and the reference voltage 10 is apt to relatively increase its level as shown at D in FIG. 4.
The oscillation output signal 104 is also supplied to a latch timing input of the D-type flipflop 13, whose data input is connected to receive the frequency-divided signal 105, so that the frequency-divided signal 105 is latched in synchronism with each falling edge of the oscillation output signal 104. Accordingly, the D-type flipflop 13 generates a bit clock 109 as shown at H in FIG. 2, which has the same frequency as that of the frequency-divided signal 105 but is delayed in phase by T/4.
The bit clock 109 is supplied to a latch timing input of the D-type flipflop 15, which receives at its data input the input data signal 101 as mentioned above. The input data signal 101 is latched in the D-type flipflop 15 at an intermediate portion of the input data signal 101 in synchronism with the rising edge of the bit clock 109, so that the D-type flipflop 15 generates a data signal 110, at I in FIG. 2. Thus, the input data signal 101 having variations caused by noise, jitter, etc. is convened to the data signal 110 having a minimized error rate.
In the above mentioned conventional bit clock regeneration circuit, it is practically difficult to cause the T/2 pulse generator 1 to generate a precise and stable T/2 pulse 103 on the basis of the input data signal 101 being supplied asynchronously.
As mentioned above, the conventional T/2 pulse generator 1 is composed of the buffers 19 and 21 in the form of an inverter, the delay circuit 20 giving a delay time of T/2, and the exclusive-OR circuit 4 as shown in FIG. 1B. Efforts have been paid to precisely generate the T/2 pulse. However, the delay circuit 20 is a discrete component, which cannot be implemented on an LSI (large-scale integrated circuit) chip. Furthermore, the delay circuit 20 is extremely expensive in comparison with the cost of the other functional units, and is too large in occupancy area and volume in view of a demand for miniaturization of devices. Accordingly, the discrete delay circuit is not preferable in practice.
On the other hand, in order to ensure that the input data signal 101 is latched in the D-type flipflop 15 at a precisely center position of the input data signal, there is required the bit clock 109 obtained by delaying the output 105 of the 1/2 frequency-divider 12 accurately by T/2. For this purpose, the duty ratio of the output 104 of the voltage controlled oscillator 11 is required to be made 50% to the utmost. However, this is difficult in the conventional circuit structure.